1. Field of the Invention
The present invention relates generally to a semiconductor device and, more particularly, to a SONOS (silicon-oxide-nitride-oxide-silicon) type non-volatile (e.g., flash) memory device having a deep well region for isolating a well region from a substrate to enhance programming and erasing operation characteristics, and related programming/erasing methods.
2. Description of the Related Art
Flash memory is non-volatile, which means that it stores data even when power is turned off. While normal EEPROM (electrically erasable and programmable read only memory) only allows one location at a time to be erased or written, flash EEPROM can operate at higher effective speeds to read and write to different locations at the same time.
Flash memory is based on floating gate type cells. Recently as device integration has advanced, there has been a strong need to reduce the size of conventional floating gate type cells.
For the above reasons, alternatives to floating gate cells have been widely studied, for example, SONOS, FeRAM, SET, NROM, etc. Among them, the SONOS cell has attracted considerable attention as next-generation cell structure for replacing a stacked floating gate cell structure.
Hereinafter, a conventional SONOS type flash memory device will be described.
FIG. 1 is a cross-sectional view showing a conventional SONOS type flash memory device. Referring to FIG. 1, the SONOS flash memory device, which may be essentially an NMOS transistor, includes a tunnel oxide layer 12, a trap nitride layer 13, a block oxide layer 14, and a gate 15 formed of N+ type polysilicon, all of which are formed on a portion of a substrate 10 and stacked in sequence. Source and drain 11 having implanted N+ type impurities are formed in the substrate 10, adjacent to both sides of the gate 15.
FIG. 2 is a cross-sectional view showing a conventional method for programming a SONOS type flash memory device. Referring to FIG. 2, bias conditions when programming the SONOS device include applying a positive voltage to both the drain 11a and the gate 15, and to ground both the source 11b and the substrate 10. Voltage applied to the gate 15 and the drain 11a creates a vertical and horizontal electric field in a direction of the length of a channel region from the source 11b to the drain 11a. By the electric field, electrons start flowing from the source 11b to the drain 11a. Then, electrons moving along the channel obtain energy enough to jump over the potential barrier of the tunnel oxide layer 12 and to enter the electron trap layer. That is, electrons are in a ‘hot’ state. Such a phenomenon may happen frequently near the drain 11a, because electrons near the drain 11a obtain relatively greater energy. Hot electrons injected into the trap nitride layer 13 are trapped therein, and therefore the threshold voltage of the SONOS flash memory device is increased.
Such a programming process is called Channel Hot Electron Injection (CHEI). During this process, an area where electrons are caught in the trap nitride layer 13 is indicated by a referential character A in FIG. 2.
In addition to CHEI, Fowler Nordheim Tunneling (F/N tunneling) may be used as programming methods of the SONOS flash memory device. At present, since F/N tunneling requires relatively higher voltage, the CHEI method is much preferred.
FIG. 3 is a cross-sectional view showing a conventional method for erasing a SONOS type flash memory device. Referring to FIG. 3, bias conditions when erasing the SONOS device include applying a positive voltage to the drain 11a and a negative voltage to the gate 15, and to ground or float both the source 11b and the substrate 10.
Under the above bias conditions, a high electric field is created in an overlapped region between the drain 11a and the gate 15, and thereby a depletion region (indicated by a referential character C) is formed near the drain 11a. In the depletion region, electron/hole pairs are produced by band-to-band tunneling. These electrons are drained to an N+ impurity region of the drain 11a. On the other hand, holes are accelerated by a lateral electric field generated in the depletion region and thereby turned into hot holes. These hot holes jump over energy barrier between the tunnel oxide layer 12 and the silicon substrate 10, and are injected into a valence band of the trap nitride layer 13. Injected hot holes are then trapped in a trap level within the trap nitride layer 13, and neutralized by reacting with electrons stored during programming, so cells are erased. Through this erasing process, the threshold voltage of the SONGS flash memory device is decreased.
Such an erasing process is called Hot Hole Injection (HHI). During this process, an area where hot holes are caught in the trap nitride layer 13 is limited to a relatively smaller local part indicated by a referential character B in FIG. 3, so erasing operation generally takes place in a smaller area than the area (A in FIG. 2) receiving hot electrons during programming operation. As a result, electrons may undesirably remain in a non-overlapped part between areas A and B.
FIG. 4 is a cross-sectional view showing a conventional method for reading a SONOS type flash memory device. Referring to FIG. 4, bias conditions when reading the SONOS device include applying a positive reference voltage to the gate 15 and a positive voltage to the source 11b, and to ground both the drain 11a and the substrate 10. Under the above bias conditions, electric current flows or not according to programming/erasing states near the drain 11a, so it is possible to read whether an operating state is programming or erasing. That is, to know whether the cell is a programming state or an erasing state is based on detection of current that flows when a reference voltage is applied to the gate. If the current is above a predefined current, the cell is in an erasing state. If the current is below the predefined current, the cell is in a programming state. Such a reading process is called Reverse Reading.
Unfortunately, the above-discussed conventional SONOS flash memory device may have the following drawbacks.
The conventional SONOS flash memory device uses Channel Hot Electron Injection programming method and Hot Hole Injection erasing method. However, in such programming/erasing methods, hot electron injecting and hot hole injecting may occur at non-coincident places, so electrons injected to locations not being neutralized by hot hole injection may accumulate in the trap layer relatively near to the center of the channel. Accordingly, the programming threshold voltage and the erasing threshold voltage may increase in comparison with the initial threshold voltages.
In addition, during an erasing operation, the non-volatile memory device may be configured to inject a number of hot holes to the trap layer roughly equivalent to the number of stored electrons. However, as discussed above, the area in which such hot holes are injected (e.g., B in FIG. 3) is smaller than the area where hot electrons are injected (e.g., A in FIG. 2). As a result, over repeated cycles of programming and erasing, hot holes may accumulate at an edge region of the trap layer, near the N+ impurity region such as the source or the drain 11a (see FIG. 3). After many cycles of programming and erasing, the accumulated charges and/or holes may adversely affect reading, programming and/or erasing operations, and may shorten the endurance of the memory device.
Endurance means the characteristic that the threshold voltage is not changed significantly or is changed only within a permissible range while the programming/erasing operations of the device are repeated. The conventional SONOS flash memory device may sometimes have a less than ideal endurance characteristic.